CMOS level shifters using native devices

ABSTRACT

A level shifter circuit configured for use between a core of a chip and input/output transistors of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.

BACKGROUND

[0001] The present invention generally relates to methods of shieldinglow voltage devices residing on high voltage domain, and morespecifically relates to using native transistors in level shifters inorder to shield low voltage devices.

[0002]FIG. 1 illustrates a typical Complementary Metal-OxideSemiconductor (CMOS) integrated circuit or chip 10, wherein an internalcore 12 is surrounded by input/output (I/O) transistors 14 (hereinafterthe “I/O”). In recent CMOS technologies (i.e., 0.25 UM, 0.18 UM, 0.13UM), the internal core 12 of a chip 10 operates at a reduced voltagecompared to the I/O 14. As a result, the internal core 12 burns lesspower (CMOS power is proportional to Vdd²), and transistors in the core12 can be scaled to smaller dimensions. Typically, digital signals inthe core 12 (which is most of the chip 10) are at 0 or VDDCORE, whiledigital signals in the I/O 14 (the smaller portion of the chip 10) areat 0 or VDDIO. As a result of the voltage difference, level shifters 16are needed between the core 12 and the I/O 14 in order to translatedigital signals from one voltage level to the other.

[0003]FIGS. 2 and 3 illustrate two traditional level shifter circuits.In FIGS. 2 and 3, “TO” refers to a voltage tolerant (“thick oxide”) I/Otransistor, while “HP” refers to a low voltage (“high performance”) coretransistor. While FIG. 2 illustrates a signal-to-gate MOS (Metal-OxideSemiconductor) level shifter, FIG. 3 illustrates a signal-to-source MOS(Metal-Oxide Semiconductor) level shifter. As shown in both FIGURES,both level shifters provide that VDDCORE (1.2V or 1.0V) is put on thegate of a voltage tolerant device (because that device's drain may go toVDDIO). As core voltages are scaled to 1.2V or even 1.0V or 0.8V, theseimplementations are becoming very slow, big, and in some cases, simplydo not function. Additionally, VDDCORE is getting too close to thevoltage threshold of the voltage tolerant device.

[0004]FIGS. 4 and 5 illustrate a common proposed solution, wherein FIG.4 corresponds to FIG. 2, and FIG. 5 corresponds to FIG. 3. As shown, thecommon proposed solution is to place a voltage regulator network in thecircuit, and then use core devices 22 as the switching elements. Thevoltage regulator network 20 consists of voltage tolerant transistors24, each having a reference voltage (“VREF”) on its gate. The referencevoltage is selected to insure that the drain of the switching devices 22cannot exceed VDDCORE.

[0005] The implementation shown in FIGS. 4 and 5 provides somedisadvantages. With regard to performance, the backbiased voltagethreshold of the regulator transistors 24 varies over temperature, VREFand process. Additionally, the reference voltage, VREF, has a similarvariability. All of the variations must be taken into account whendesigning the circuit, thus nominal performance must be degraded.Furthermore, the reference generator (which generates VREF) draws directcurrent (DC) power. Hence, in order to avoid routing high voltagesignals in the core, a VREF generator must be implemented into every I/Ofunction, and the reference generators consume silicon area. The voltagereference (VREF) must be greater than VDDCORE (i.e., VDDCORE+VTLIN)because the voltage regulator devices 24 have such high voltagethresholds.

OBJECTS AND SUMMARY

[0006] A general object of an embodiment of the present invention is toshield low voltage devices residing on high voltage domain.

[0007] Another object of an embodiment of the present invention is touse native transistors in level shifters in order to shield low voltagedevices residing on high voltage domain.

[0008] Still another object of an embodiment of the present invention isto shield low voltage devices residing on high voltage domain withouthaving to use a reference voltage.

[0009] Yet another object of an embodiment of the present invention isto shield low voltage devices residing on high voltage domain by usingVDDCORE on the gate of a voltage tolerant, native device.

[0010] Briefly, and in accordance with at least one of the forgoingobjects, an embodiment of the present invention provides a level shiftercircuit configured for use between a core of a chip and input/outputtransistors of the chip in order to shield low voltage devices residingon the core. The level shifter circuit includes voltage tolerant nativedevices which have VDDCORE on their gates, and each voltage tolerantnative device is cascoded with a low voltage transistor on the core.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The organization and manner of the structure and operation of theinvention, together with further objects and advantages thereof, maybest be understood by reference to the following description, taken inconnection with the accompanying drawings, wherein like referencenumerals identify like elements in which:

[0012]FIG. 1 is a schematic diagram of a conventional CMOS integratedcircuit, wherein an internal core is surrounded by a ring ofinput/output (I/O) transistors;

[0013]FIG. 2 is a schematic diagram of a conventional signal-to-gate MOSlevel shifter;

[0014]FIG. 3 is a schematic diagram of a conventional signal-to-sourceMOS level shifter;

[0015]FIGS. 4 and 5 are schematic diagrams of conventionalimplementations which correspond to FIGS. 2 and 3, respectively, whereineach of the implementations provides that a voltage regulator device isimplemented in the circuit, and core devices are used as the switchingelements;

[0016]FIGS. 6 and 7 are schematic diagrams of implementations which arein accordance with an embodiment of the present invention; and

[0017]FIGS. 8 and 9 are implementations similar to that of FIGS. 6 and7, respectively, but wherein additional drain protection is included.

DESCRIPTION

[0018] While the invention may be susceptible to embodiment in differentforms, there are shown in the drawings, and herein will be described indetail, specific embodiments with the understanding that the presentdisclosure is to be considered an exemplification of the principles ofthe invention, and is not intended to limit the invention to that asillustrated and described herein.

[0019] FIGS. 6-9 illustrate level shifter circuit implementations whichcan be used in association with a chip 10 as shown in FIG. 1 to shieldlow voltage devices residing on the core 12. Specifically, FIG. 6corresponds to FIGS. 2 and 4, and illustrates a signal-to-gate MOS levelshifter which is in accordance with an embodiment of the presentinvention and is configured for use between the core of a chip and theI/O of a chip (see FIG. 1). FIG. 7 corresponds to FIGS. 3 and 5, andillustrates a signal-to-source MOS level shifter which is in accordancewith an embodiment of the present invention and is configured for usebetween a core of a chip and the I/O of a chip (see FIG. 1). FIGS. 8 and9 are similar to FIGS. 6 and 7, respectively, but include additionaldrain protection.

[0020] As shown in FIGS. 6-9, each of the implementations includes aregulator network 40, 42, and each regulator network 40, 42 includesvoltage tolerant native devices or transistors 44. Each of the devices44 has a gate, and instead of having a reference voltage on the gate (asshown in FIGS. 4 and 5), VDDCORE (“VDD12”) is on the gates of thevoltage tolerant native devices 44. Each of the voltage tolerant nativedevices 44 is cascoded with one or more high performance, low voltagetransistors 46 on the core 12 (see FIG. 1). Preferably, each of thevoltage tolerant native devices 44 comprises a low voltage tolerant NMOSdevice. The voltage tolerant native devices shield low voltage deviceswhich reside on the high voltage power domain (i.e., core) of a chip(see FIG. 1).

[0021] Preferably, each of the voltage tolerant native devices 44 has ashort gate length, has a nearly zero threshold voltage, and isrelatively fast (i.e., Ldrawn ˜0.30 to 1.0). The level shifters shown inFIGS. 6-9 are configured to shift voltages from low voltage core CMOSlevels to high voltage I/O CMOS levels.

[0022] In the circuits shown in FIGS. 6 and 7, the drain voltage of theswitching element 46 can go slightly above VDDCORE. The drain voltagewill rise until the sub-threshold current through the regulator device44 equals the sub-threshold current through the switching device 46.Most MOS devices are slightly more drain voltage tolerant than gatevoltage tolerant, so this should not be problem. However, if in a giventechnology it is a problem, as shown in FIGS. 8 and 9, the voltagetolerant native devices 44 can be, cascoded with a high performance, lowvoltage transistor 48, thus limiting the voltage exposure on both highperformance, low voltage transistors 46 and 48. In this case, as shownin FIGS. 8 and 9, the voltage tolerant native devices 44 are connectedin series to the high performance, low voltage transistors 48.

[0023] The implementations illustrated in FIGS. 6-9 provide that novoltage reference (VREF) generation circuit is required, and this savesarea and power. Additionally, there are no potential reliability issueswith regard to the instability in a reference voltage (i.e., VREF), suchas due to model inaccuracy, temperature, VDD drift, and variations inthe voltage threshold of the regulator devices 44. Additionally, thereis no need to design around voltage reference and voltage thresholdtolerances.

[0024] While embodiments of the present invention are shown anddescribed, it is envisioned that those skilled in the art may devisevarious modifications of the present invention without departing fromthe spirit and scope of the appended claims.

What is claimed is:
 1. A level shifter circuit configured for usebetween a core of a chip and input/output transistors of the chip inorder to shield low voltage devices residing on the core, said levelshifter circuit comprising voltage tolerant native devices, each havinga gate, VDDCORE on the gates of the voltage tolerant native devices. 2.A level shifter circuit as defined in claim 1, wherein each voltagetolerant native device is cascoded with a low voltage transistor on thecore.
 3. A level shifter circuit as defined in claim 1, wherein saidvoltage tolerant native devices are comprised of NMOS (N-channelMetal-Oxide Semiconductor) devices.
 4. A level shifter circuit asdefined in claim 1, wherein each of said voltage tolerant native deviceshas a short gate length.
 5. A level shifter circuit as defined in claim1, wherein each of said voltage tolerant native devices has a thresholdvoltage which is near zero.
 6. A level shifter circuit as defined inclaim 1, wherein each of the low voltage transistors on the core withwhich said voltage tolerant native devices are cascoded has a gate, andVDDCORE is on the gate of each of the the low voltage transistors on thecore with which said voltage tolerant native devices are cascoded.
 7. Alevel shifter circuit as defined in claim 1, wherein said level shiftercircuit is configured to shift voltages from low voltage core CMOSlevels to high voltage I/O CMOS levels.
 8. A level shifter circuit asdefined in claim 1, wherein said level shifter circuit saves area andpower because no reference voltage generator is needed to provide areference voltage to the voltage tolerant native devices.
 9. A levelshifter circuit as defined in claim 1, wherein said level shiftercircuit provides increased performance because variations in referencevoltage and the voltage threshold of the voltage tolerant native devicesacross process, voltage, and temperature do not need to be accountedfor.
 10. A level shifter circuit as defined in claim 1, wherein saidlevel shifter circuit is less sensitive to power squelching.
 11. A levelshifter circuit as defined in claim 1, wherein said level shiftercircuit is scalable to very low core voltage levels.
 12. A level shiftercircuit as defined in claim 1, further comprising drain protectionwherein said voltage tolerant native devices are cascoded with lowvoltage transistors to provide a regulator network, said regulatornetwork cascoded with low voltage transistors on the core.
 13. A chipcomprising: a core; input/output transistors; and at least one levelshifter circuit between said core and said input/output transistors,said level shifter circuit configured to shield low voltage devicesresiding on said core, said level shifter circuit comprising voltagetolerant native devices, each having a gate, VDDCORE on the gates of thevoltage tolerant native devices.
 14. A chip as defined in claim 13,wherein each voltage tolerant native device is cascoded with a lowvoltage transistor on the core.
 15. A chip as defined in claim 13,wherein said voltage tolerant native devices are comprised of NMOS(N-channel Metal-Oxide Semiconductor) devices.
 16. A chip as defined inclaim 13, wherein each of said voltage tolerant native devices has ashort gate length.
 17. A chip as defined in claim 13, wherein each ofsaid voltage tolerant native devices has a threshold voltage which isnear zero.
 18. A chip as defined in claim 13, wherein each of the lowvoltage transistors on the core with which said voltage tolerant nativedevices are cascoded has a gate, and VDDCORE is on the gate of each ofthe the low voltage transistors on the core with which said voltagetolerant native devices are cascoded.
 19. A chip as defined in claim 13,wherein said level shifter circuit is configured to shift voltages fromlow voltage core CMOS levels to high voltage I/O CMOS levels.
 20. A chipas defined in claim 13, wherein said level shifter circuit saves areaand power because no reference voltage generator is needed to provide areference voltage to the voltage tolerant native devices.
 21. A chip asdefined in claim 13, wherein said level shifter circuit providesincreased performance because variations in reference voltage and thevoltage threshold of the voltage tolerant native devices across process,voltage, and temperature do not need to be accounted for.
 22. A chip asdefined in claim 13, further comprising drain protection wherein saidvoltage tolerant native devices are cascoded with low voltagetransistors to provide a regulator network, said regulator networkcascoded with low voltage transistors on the core.